1. Field of the Invention
The present invention relates to memory devices, and more particularly, to a redundancy decoding circuit having an automatic deselection feature for reducing power consumption in a semiconductor memory device.
2. Description of the Related Art
As the integration density of VLSI memory devices increases, the probability of encountering a defective memory cell also increases. To prevent a reduction in the yield rate due to defective cells, redundancy schemes are used to replace defective memory cells in devices having a limited number of defective cells. Examples of redundancy schemes can be found in U.S. Pat. Nos. 5,471,426 and 5,146,429.
FIG. 1 is a circuit diagram of a conventional redundancy decoding circuit 100 which is used to decode redundancy cells that are used in place of defective cells in a memory device. The redundancy decoding circuit 100 of FIG. 1 includes a comparator 10, which includes internal fuses F1-F4, N-channel metal-oxide semiconductor (NMOS) transistors MN1-MN4, and inverters INV1 and INV2. Comparator 10 decodes a redundant address which is applied through input terminals A1B and A2B responsive to the status of internal fuses F1-F4, thereby generating a redundancy activation status signal (REDB) at output terminal N1.
The redundancy decoding circuit 100 of FIG. 1 also includes a drive circuit which includes two P-channel metal-oxide semiconductor (PMOS) transistors MP1 and MP2, and an NMOS transistor MN5. The drive circuit supplies the drive current to the output terminal N1 of comparator 10. A deselect signal DESEL, which is received from a latch L2 from inverters INV4 and INV5, is applied to the gates of transistor MP2 and MN5.
The redundancy decoding circuit 100 of FIG. 1 further includes a switching control signal generator which includes a master fuse MF and a high impedance resistor R1 connected in series with MF between a power supply voltage VCC and a ground voltage VSS. Resistor R1 is fabricated from a polysilicon material. The switching control signal generator generates a switching control signal which is applied to gate of transistor MP1, thereby allowing the drive circuit to drive the comparator 10.
The master fuse MF, along with appropriate ones of the internal fuses F1-F4, can be cut using a laser beam or high voltage while the semiconductor memory device is still in the wafer state. To enable the redundancy decoding circuit 100 of FIG. 1 to decode a redundant cell instead of a defective memory cell, master fuse MF must be cut, thereby allowing resistor R1 to pull the gate of MP1 down to the low logic level. This allows the drive circuit to supply a drive current from the power supply voltage VCC to the output terminal N1 when the deselect signal DESEL is pulled low. The comparator 10 then decodes an address applied through the redundant address input terminals A1B and A2B, thereby generating a redundancy activation status signal REDB at output terminal N1 for decoding a redundant memory cell depending upon which of the internal fuses F1-F4 are cut.
To reduce standby current during standby mode in a semiconductor memory device used in a battery-powered electronics system, the frequency of a clock signal can be reduced to zero (i.e., the clock signal does not transition). An example of a synchronous burst static random access memory (SRAM) in which the clock signal can be stopped is disclosed in Samsung specification "KM736V687" for a 64K.times.36 synchronous SRAM, revision 1.0, May 1997, which is hereby incorporated by reference. Hereinafter, when the clock frequency is zero, the standby mode will be referred to as "stop mode" or "stop clock mode". A problem with the conventional redundancy decoding circuit 100 described above is that a DC current path can exist during stop mode as will be described more fully below with reference to FIG. 2A which is a timing diagram illustrating signals at various points in FIG. 1 when the decoding circuit transitions from a deselect mode to a stop mode, and FIG. 2B, which is a timing diagram illustrating the signals when the circuit of FIG. 1 transitions from a normal read/write mode to stop mode.
Referring to FIG. 2A, when the semiconductor memory device is deselected, that is, the chip select signal CSB switches from low to high, the signal CSB is transferred to latch L2 through transmission gates TG1 and TG2 which are controlled by control signals BI and BIB. Latch L2 outputs the deselect signal DESEL at a high logic level, which turns transistor MP2 off. Under these conditions, when a semiconductor memory device having the decoding circuit of FIG. 1 enters stop mode, there is no DC current path through the redundancy decoding circuit even though master fuse MF is open.
However, if the semiconductor memory device enters stop mode after a normal read/write operation as shown in FIG. 2B, the chip select signal CSB is latched at a low level into latch L2 by control signals BI and BIB, thereby driving the deselect signal DESEL low. A normal read/write operation is performed in a manner known in the art, after which the device enters stop mode. Under these conditions, namely, the master fuse MF is disconnected, and the deselect signal DESEL is at a low level, a DC current path including transistors MP1, MP2, and any of fuses F1-F4 which are not cut, exists in the decoding circuit 100 of FIG. 1 during stop mode. This causes standby current to increase during stop mode.